One or more embodiments relate to a method of controlling an operation of a flash memory device and, more particularly, to a method of controlling an operation of a flash memory device, which is capable of efficiently controlling a memory cell having a shifted threshold voltage after repetitive program and erase operations are performed.
In recent years, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and do not require the refresh function of rewriting data at specific intervals. In order to develop large capacity memory devices capable of storing a lot of data, active research is being carried out on technologies for the high degree of integration of memory devices. Here, a program operation refers to an operation of writing data into a memory cell, and an erase operation refers to an operation of erasing data written into a memory cell.
For the high degree of integration of memory devices, a NAND flash memory device in which a number of memory cells are coupled in series (i.e., a structure in which a drain or a source is shared by neighboring cells), thereby constituting one string, has been developed. The NAND flash memory device is a memory device configured to sequentially read data unlike a NOR flash memory device. The program and erase operations of this NAND flash memory device are performed by controlling the threshold voltage Vt of a memory cell while electrons are injected into or discharged from a floating gate using the F-N tunneling.
In the NAND flash memory device, it is important to secure the reliability of a memory cell. In particular, the data retention characteristic of a memory cell is emerging as an important problem. As described above, however, the program and erase operations of the NAND flash memory device are performed using the F-N tunneling method. During the repetitive F-N tunneling processes, electrons are trapped at the tunnel oxide layer of a memory cell and the threshold voltage of the memory cell shifts. Accordingly, when data is read, data stored in an original memory cell is erroneously read. That is, reliability of the memory cell is deteriorated.
A shift in the threshold voltage of the memory cell is generated by the electrons trapped at the tunnel oxide layer resulting from the repetitive F-N tunneling process according to program cycles. The term ‘program cycles’ refers to a process of repetitively performing the program operation and the erase operation. In order to prevent a shift in the threshold voltage of the memory cell, a method of sufficiently reducing an erase voltage to a verification voltage or less by controlling a bias condition (i.e., a bias voltage) during the program operation and the erase operation is used. In this method, however, the threshold voltage shifts because it is increased by as much as an increased bias voltage. Another method of preventing a shift in the threshold voltage of the memory cell is to reduce the amount of electrons trapped upon F-N tunneling by reducing the thickness of the tunnel oxide layer. However, the method of reducing the thickness of the tunnel oxide layer is limited due to the data retention characteristic problem or a read disturbance problem.
Prior to the method of reducing a shift in the threshold voltage of the memory cell, it is very important to monitor a shift in the threshold voltage of the memory cell. In general, in the case of a 1-bit cell, the threshold voltage of a memory cell becomes positive in a program state, and the threshold voltage of a memory cell becomes negative in an erase state. However, in a 2- to 4-bit multi-level cell (MLC) in which the distributions of a threshold voltage of a memory cell are further subdivided in order to store a greater amount of data in a single memory cell, threshold voltage distribution margin tends to abruptly decrease. In the case where a threshold voltage distribution of the memory cell is changed by program cycles as compared with its initial stage, if a conventional fixed read voltage level is continuously used, data stored in the memory cell is more likely to be erroneously read.
This issue may also occur in a program operation. The program operation for a memory cell may be performed using an incremental step pulse program (ISPP) method. In this ISPP method, when a program operation is performed, voltage applied to a memory cell begins from a start bias and is stepped up as much as a specific step bias. If a program operation is performed using this ISPP method, an over-program problem can be prevented. However, if the threshold voltage of a memory cell rises because of a shift according to program cycles, the over-program problem can be generated although the ISPP method is used.
It is therefore important to monitor a shift in the threshold voltage of a memory cell prior to a method of reducing a shift in the threshold voltage of the memory cell.